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| 1 LTC1966 sn1966 1966fas precision micropower, ds rms-to-dc converter n no-hassle simplicity: true rms-dc conversion with only one external capacitor delta sigma conversion technology n high accuracy: 0.1% gain accuracy from 50hz to 1khz 0.25% total error from 50hz to 1khz n high linearity: 0.02% linearity allows simple system calibration n low supply current: 155 m a typ, 170 m a max n ultralow shutdown current: 0.1 m a n constant bandwidth: independent of input voltage 800khz C3db, 6khz 1% n flexible supplies: 2.7v to 5.5v single supply up to 5.5v dual supply n flexible inputs: differential or single ended rail-to-rail common mode voltage range up to 1v peak differential voltage n flexible output: rail-to-rail output separate output reference pin allows level shifting n small size: space saving 8-pin msop package n true rms digital multimeters and panel meters n true rms ac + dc measurements descriptio u features applicatio s u the ltc ? 1966 is a true rms-to-dc converter that utilizes an innovative patented ds computational technique. the internal delta-sigma circuitry of the LTC1966 makes it sim- pler to use, more accurate, lower power and dramatically more flexible than conventional log-antilog rms-to-dc converters. the LTC1966 accepts single ended or differential input signals (for emi/rfi rejection) and supports crest factors up to 4. common mode input range is rail-to-rail. differ- ential input range is 1v peak , and offers unprecedented lin- earity. unlike previously available rms-to-dc converters, the superior linearity of the LTC1966 allows hassle-free system calibration at any input voltage. the LTC1966 also has a rail-to-rail output with a separate output reference pin providing flexible level shifting. the LTC1966 operates on a single power supply from 2.7v to 5.5v or dual supplies up to 5.5v. a low power shutdown mode reduces supply current to 0.5 m a. the LTC1966 is insensitive to pc board soldering and stresses, as well as operating temperature. the LTC1966 is packaged in the space-saving msop package which is ideal for portable applications. single supply rms-to-dc converter c ave 1 f v out + 1966 ta01 2.7v to 5.5v output differential input LTC1966 v dd 0.1 f opt. ac coupling v ss en gnd out rtn in1 in2 typical applicatio u v in (mv ac rms ) ?.0 linearity error (v out mv dc ?v in mv ac rms ) ?.6 ?.2 0.2 ?.8 ?.4 0 100 200 300 400 1966 ta01b 500 50 0 150 250 350 450 LTC1966, ? s 60hz sinewaves conventional log/antilog quantum leap in linearity performance , ltc and lt are registered trademarks of linear technology corporation. protected under u.s. patent numbers 6,359,576 and 6,362,677
2 LTC1966 sn1966 1966fas supply voltage v dd to gnd .............................................. C 0.3 to 7v v dd to v ss ............................................ C 0.3v to 12v v ss to gnd ............................................. C 7v to 0.3v input currents (note 2) ..................................... 10ma output current (note 3) ..................................... 10ma enable voltage ..................... v ss C 0.3v to v ss + 12v out rtn voltage .............................. v ss C 0.3v to v dd operating temperature range (note 4) LTC1966c/LTC1966i ......................... C 40 c to 85 c specified temperature range (note 5) LTC1966c/LTC1966i ......................... C 40 c to 85 c maximum junction temperature ......................... 150 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c order part number LTC1966cms8 LTC1966ims8 t jmax = 150 c, q ja = 220 c/ w absolute axi u rati gs w ww u package/order i for atio uu w (note 1) ms8 part marking lttg ltth 1 2 3 4 gnd in1 in2 v ss 8 7 6 5 enable v dd out rtn v out top view ms8 package 8-lead plastic msop the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v dd = 5v, v ss = C 5v, v outrtn = 0v, c ave = 10 m f, v in = 200mv rms , v enable = 0.5v unless otherwise noted. electrical characteristics consult ltc marketing for parts specified with wider operating temperature ranges. symbol parameter conditions min typ max units conversion accuracy g err conversion gain error 50hz to 1khz input (notes 6, 7) 0.1 0.3 % l 0.4 % v oos output offset voltage (notes 6, 7) 0.1 0.2 mv l 0.4 mv lin err linearity error 50mv to 350mv (notes 7, 8) l 0.02 0.15 % psrr power supply rejection (note 9) 0.02 0.15 %/v l 0.20 %/v v ios input offset voltage (notes 6, 7, 10) 0.2 0.8 mv l 1.0 mv accuracy vs crest factor (cf) cf = 4 60hz fundamental, 200mv rms (note 11) l C1 2 mv cf = 5 60hz fundamental, 200mv rms (note 11) l C20 30 mv input characteristics i vr input voltage range l v ss v dd v z in input impedance average, differential (note 12) 8 m w average, common mode (note 12) 100 m w cmrri input common mode rejection (note 13) l 7 200 m v/v v imax maximum input swing accuracy = 1% (note 14) l 1 1.05 v v imin minimum rms input l 5mv psrri power supply rejection v dd supply (note 9) l 250 600 m v/v v ss supply (note 9) l 120 300 m v/v 3 LTC1966 sn1966 1966fas the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v dd = 5v, v ss = C 5v, v outrtn = 0v, c ave = 10 m f, v in = 200mv rms , v enable = 0.5v unless otherwise noted. electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the inputs (in1, in2) are protected by shunt diodes to v ss and v dd . if the inputs are driven beyond the rails, the current should be limited to less than 10ma. note 3: the LTC1966 output (v out ) is high impedance and can be overdriven, either sinking or sourcing current, to the limits stated. note 4: the LTC1966c/LTC1966i are guaranteed functional over the operating temperature range of C 40 c to 85 c. note 5: the LTC1966c is guaranteed to meet specified performance from 0 c to 70 c. the LTC1966c is designed, characterized and expected to meet specified performance from C 40 c to 85 c but is not tested nor qa sampled at these temperatures. the LTC1966i is guaranteed to meet specified performance from C 40 c to 85 c. note 6: high speed automatic testing cannot be performed with c ave = 10 m f. the LTC1966 is 100% tested with c ave = 22nf. correlation tests have shown that the performance limits above can be guaranteed with the additional testing being performed to guarantee proper operation of all the internal circuitry. note 7: high speed automatic testing cannot be performed with 60hz inputs. the LTC1966 is 100% tested with dc and 10khz input signals. measurements with dc inputs from 50mv to 350mv are used to calculate the four parameters: g err , v oos , v ios and linearity error. correlation tests have shown that the performance limits above can be guaranteed with the additional testing being performed to guarantee proper operation of all internal circuitry. note 8: the LTC1966 is inherently very linear. unlike older log/antilog circuits, its behavior is the same with dc and ac inputs, and dc inputs are used for high speed testing. note 9: the power supply rejections of the LTC1966 are measured with dc inputs from 50mv to 350mv. the change in accuracy from v dd = 2.7v to v dd = 5.5v with v ss = 0v is divided by 2.8v. the change in accuracy from v ss = 0v to v ss = C5.5v with v dd = 5.5v is divided by 5.5v. note 10: previous generation rms-to-dc converters required nonlinear input stages as well as a nonlinear core. some parts specify a dc reversal error, combining the effects of input nonlinearity and input offset voltage. the LTC1966 behavior is simpler to characterize and the input offset voltage is the only significant source of dc reversal error. symbol parameter conditions min typ max units output characteristics ovr output voltage range l v ss v dd v z out output impedance (note 12) l 75 85 95 k w cmrro output common mode rejection (note 13) l 16 200 m v/v v omax maximum differential output swing accuracy = 2%, dc input (note 14) 1.0 1.05 v l 0.9 v psrro power supply rejection v dd supply (note 9) l 250 1000 m v/v v ss supply (note 9) l 50 500 m v/v frequency response f 1p 1% additional error (note 15) c ave = 10 m f6khz f 10p 10% additional error (note 15) c ave = 10 m f20khz f C 3db 3db frequency (note 15) 800 khz power supplies v dd positive supply voltage l 2.7 5.5 v v ss negative supply voltage (note 16) l C 5.5 0 v i dd positive supply current in1 = 20mv, in2 = 0v l 155 170 m a in1 = 200mv, in2 = 0v 158 m a i ss negative supply current in1 = 20mv, in2 = 0v l 12 20 m a shutdown characteristics i dds supply currents v enable = 4.5v l 0.5 10 m a i sss supply currents v enable = 4.5v l C1 C0.1 m a i ih enable pin current high v enable = 4.5v l C 0.3 C 0.05 m a i il enable pin current low v enable = 0.5v l C2 C1 C0.1 m a v th enable threshold voltage v dd = 5v, v ss = C 5v 2.4 v v dd = 5v, v ss = gnd 2.1 v v dd = 2.7v, v ss = gnd 1.3 v v hys enable threshold hysteresis 0.1 v 4 LTC1966 sn1966 1966fas electrical characteristics note 11: high speed automatic testing cannot be performed with 60hz inputs. the LTC1966 is 100% tested with dc stimulus. correlation tests have shown that the performance limits above can be guaranteed with the additional testing being performed to verify proper operation of all internal circuitry. note 12: the LTC1966 is a switched capacitor device and the input/output impedance is an average impedance over many clock cycles. the input impedance will not necessarily lead to an attenuation of the input signal measured. refer to the applications information section titled input impedance for more information. note 13: the common mode rejection ratios of the LTC1966 are measured with dc inputs from 50mv to 350mv. the input cmrr is defined as the change in v ios measured between input levels of v ss to v ss + 350mv and input levels of v dd C 350mv to v dd divided by v dd C v ss C 350mv. the output cmrr is defined as the change in v oos measured with out rtn = v ss and out rtn = v dd C 350mv divided by v dd C v ss C 350mv. typical perfor a ce characteristics uw note 14: the LTC1966 input and output voltage swings are limited by internal clipping. however, its ds topology is relatively tolerant of momentary internal clipping. the input clipping is tested with a crest factor of 2, while the output clipping is tested with a dc input. note 15: the LTC1966 exploits oversampling and noise shaping to reduce the quantization noise of internal 1-bit analog-to-digital conversions. at higher input frequencies, increasingly large portions of this noise are aliased down to dc. because the noise is shifted in frequency, it becomes a low frequency rumble and is only filtered at the expense of increasingly long settling times. the LTC1966 is inherently wideband, but the output accuracy is degraded by this aliased noise. these specifications apply with c ave = 10 m f and constitute a 3-sigma variation of the output rumble. note 16: the LTC1966 can operate down to 2.7v single supply but cannot operate at 2.7v. this additional constraint on v ss can be expressed mathematically as C 3 ? (v dd C 2.7v) v ss ground. gain and offset vs output common mode gain and offset vs output common mode output common mode (v) 0 0.5 gain error (%) offset voltage (mv) 0.4 0.2 0.1 0 0.5 0.2 1.0 2.0 2.5 5.0 4.5 1966 g05 0.3 0.3 0.4 0.1 0.5 0.4 0.2 0.1 0 0.5 0.2 0.3 0.3 0.4 0.1 0.5 1.5 3.0 3.5 4.0 v dd = 5v v ss = gnd v ios v oos gain error output common mode (v) ? 0.5 gain error (%) offset voltage (mv) 0.4 0.2 0.1 0 0.5 0.2 ? ? 05 4 1966 g06 0.3 0.3 0.4 0.1 0.5 0.4 0.2 0.1 0 0.5 0.2 0.3 0.3 0.4 0.1 ? 2 1 2 3 v dd = 5v v ss = 5v v ios v oos gain error gain and offset vs input common mode gain and offset vs input common mode input common mode (v) 0 0.5 gain error (%) offset voltage (mv) 0.4 0.2 0.1 0 0.5 0.2 1.0 2.0 2.5 5.0 4.5 1966 g02 0.3 0.3 0.4 0.1 0.5 0.4 0.2 0.1 0 0.5 0.2 0.3 0.3 0.4 0.1 0.5 1.5 3.0 3.5 4.0 v dd = 5v v ss = gnd v ios v oos gain error input common mode (v) ? 0.5 gain error (%) offset voltage (mv) 0.4 0.2 0.1 0 0.5 0.2 ? ? 05 4 1966 g03 0.3 0.3 0.4 0.1 0.5 0.4 0.2 0.1 0 0.5 0.2 0.3 0.3 0.4 0.1 ? ? 1 2 3 v dd = 5v v ss = 5v v ios v oos gain error 5 LTC1966 sn1966 1966fas typical perfor a ce characteristics uw gain and offset vs v ss supply v ss (v) ? 0.5 gain error (%) offset voltage (mv) 0.4 0.2 0.1 0 0.5 0.2 ? ? 0 1966 g11 0.3 0.3 0.4 0.1 0.5 0.4 0.2 0.1 0 0.5 0.2 0.3 0.3 0.4 0.1 ? ? ? v dd = 5v v ios v oos gain error nominal specified conditions gain and offsets vs temperature temperature ( c) ?0 0.5 gain error (%) offset voltage (mv) 0.4 0.2 0.1 0 0.5 0.2 ?5 0 125 1966 g07 0.3 0.3 0.4 0.1 ?.0 0.8 0.4 0.2 0 1.0 0.4 0.6 0.6 0.8 0.2 50 25 75 100 v dd = 2.7v v ss = gnd v ios v oos gain error gain and offset vs input common mode gain and offset vs output common mode input common mode (v) 0 0.5 gain error (%) offset voltage (mv) 0.4 0.2 0.1 0 0.5 0.2 0.6 1.2 1.5 2.7 1966 g01 0.3 0.3 0.4 0.1 ?.0 0.8 0.4 0.2 1.0 0.4 0.6 0.6 0.8 0.2 0 0.3 0.9 1.8 2.1 2.4 v dd = 2.7v v ss = gnd v ios v oos gain error output common mode (v) 0 0.5 gain error (%) offset voltage (mv) 0.4 0.2 0.1 0 0.5 0.2 0.6 1.2 1.5 2.7 1966 g04 0.3 0.3 0.4 0.1 ?.0 0.8 0.4 0.2 1.0 0.4 0.6 0.6 0.8 0.2 0 0.3 0.9 1.8 2.1 2.4 v dd = 2.7v v ss = gnd v ios v oos gain error gain and offsets vs temperature temperature ( c) ?0 0.5 gain error (%) offset voltage (mv) 0.4 0.2 0.1 0 0.5 0.2 ?5 0 125 1966 g08 0.3 0.3 0.4 0.1 0.5 0.4 0.2 0.1 0 0.5 0.2 0.3 0.3 0.4 0.1 50 25 75 100 v dd = 5v v ss = gnd v ios v oos gain error gain and offsets vs temperature temperature ( c) ?0 0.5 gain error (%) offset voltage (mv) 0.4 0.2 0.1 0 0.5 0.2 ?5 0 125 1966 g09 0.3 0.3 0.4 0.1 0.5 0.4 0.2 0.1 0 0.5 0.2 0.3 0.3 0.4 0.1 50 25 75 100 v dd = 5v v ss = 5v v ios v oos gain error 6 LTC1966 sn1966 1966fas v in1 (mv) 500 v outdc ?|v indc | (mv) 0.02 0.06 0.10 300 1966 g14 0.02 0.06 0 0.04 0.08 0.04 0.08 0.10 300 ?00 100 500 effect of offsets may be positive or negative c ave = 1 f v in2 = gnd typical perfor a ce characteristics uw performance vs large crest factors ac linearity dc linearity crest factor 1 output voltage (mv dc) 220 4 1966 g12 190 170 23 5 160 150 230 210 200 180 678 200mv rms scr waveforms c ave = 4.7 f v dd = 5v 5%/div 20hz 100hz 60hz 250hz fundamental frequency v in1 (mv ac rms ) 0 v out (mv dc) ?v in (mv ac rms ) 0.20 0.15 0.10 0.05 0 0.05 0.10 0.15 0.20 400 1966 g13 100 200 300 500 350 50 150 250 450 60hz sinewaves c ave = 1 f v in2 = gnd quiescent supply currents vs supply voltage quiescent supply currents vs temperature v dd supply voltage (v) 0 ?5 supply current ( a) 0 50 75 100 4 200 1966 g16 25 26 3 15 125 150 175 v ss = gnd i dd i ss temperature ( c) ?0 i dd ( a) i ss ( a) 160 25 1966 g17 130 ?5 0 50 170 150 140 15 0 10 5 75 100 125 v dd = 5v, v ss = 5v v dd = 5v, v ss = 5v v dd = 5v, v ss = gnd v dd = 5v, v ss = gnd v dd = 2.7v, v ss = gnd v dd = 2.7v, v ss = gnd shutdown currents vs enable voltage enable pin voltage (v) 0 250 200 i dd i en 150 100 50 0 ?0 ?00 500 250 0 250 500 35 1966 g18 12 46 supply current ( a) enable pin current (na) v dd = 5v i ss input signal bandwidth input signal frequency (hz) 100 1k output dc voltage (mv) 10 1000 10k 100k 1m 1966 g19 1 100 0.1% error 1% error 10% error 3db performance vs crest factor crest factor 1.0 199.8 output voltage (mv dc) 200.0 200.2 200.4 200.6 2.0 3.0 4.0 5.0 1966 g15 200.8 201.0 1.5 2.5 3.5 4.5 20hz 60hz 100hz 200mv rms scr waveforms c ave = 10 f v dd = 5v o.1%/div gain and offset vs v dd supply v dd (v) 2.5 0.5 gain error (%) offset voltage (mv) 0.4 0.2 0.1 0 0.5 0.2 3.0 3.5 5.5 1966 g10 0.3 0.3 0.4 0.1 ?.0 0.8 0.4 0.2 0 1 0.4 0.6 0.6 0.8 0.2 4.5 4.0 5.0 v ss = gnd v ios v oos gain error 7 LTC1966 sn1966 1966fas typical perfor a ce characteristics uw bandwidth to 100khz dc transfer function near zero v in1 (mv dc) ?0 v out (mv dc) 10 20 20 1966 g22 0 ?0 ?0 0 10 ?5 ? 5 15 30 5 15 ? 25 v in2 = gnd three representitive units common mode rejection ratio vs frequency frequency (hz) 40 common mode rejection ratio (db) 50 70 80 100 110 10 1k 10k 1m 1966 g23 30 100 100k 90 60 20 v dd = 5v v ss = ?v 5v input conversion to dc output output accuracy vs signal amplitude input signal bandwidth input frequency (khz) 1 190 output dc voltage (mv) 192 194 196 198 10 100 1000 1966 g20 188 186 184 182 200 202 1%/div c ave = 2.2 f input frequency (khz) 0 195 output dc voltage (mv) 196 198 199 200 202 10 50 70 1966 g21 197 201 40 90 100 20 30 60 80 0.5%/div c ave = 47 f v in1 (v rms ) 0 ?0 v out (mv dc) ?v in (mv rms ) ?5 ?0 ? 0 5 10 0.5 1 1.5 2 1966 g24 2.5 1% error ac inputs = 60hz sinewaves v in2 = gnd 1% error ac input v dd = 3v ac input v dd = 5v dc input v dd = 5v 8 LTC1966 sn1966 1966fas gnd (pin 1): ground. a power return pin. in1 (pin 2): differential input. dc coupled (polarity is irrelevant). in2 (pin 3): differential input. dc coupled (polarity is irrelevant). v ss (pin 4): negative voltage supply. gnd to C 5.5v. v out (pin 5): output voltage. this is high impedance. the rms averaging is accomplished with a single shunt ca- pacitor from this node to out rtn. the transfer function is given by: v out rtn average in in out () = () ? ? 21 2 uu u pi fu ctio s out rtn (pin 6): output return. the output voltage is created relative to this pin. the v out and out rtn pins are not balanced and this pin should be tied to a low imped- ance, both ac and dc. although it is typically tied to gnd, it can be tied to any arbitrary voltage, v ss < out rtn < (v dd C max output). best results are obtained when out rtn = gnd. v dd (pin 7): positive voltage supply. 2.7v to 5.5v. enable (pin 8): an active-low enable input. LTC1966 is debiased if open circuited or driven to v dd . for normal operation, pull to gnd, a logic low or even v ss . 9 LTC1966 sn1966 1966fas applicatio s i for atio wu uu start not sure no no 1966 ta02 do you need true rms-to-dc conversion? read rms-to-dc conversion no no yes yes yes no no yes yes yes do you have any LTC1966s yet? did you already try out the LTC1966? did your circuit work? now does your rms circuit work well enough that you are ready to buy the LTC1966? do you want to know how to use the LTC1966 first? contact ltc by phone or at www.linear.com and get some now read the troubleshooting guide. if necessary, call ltc for applications support contact ltc and place your order read the design cookbook read the troubleshooting guide again or call ltc for applications support find someone who does and give them this data sheet 10 LTC1966 sn1966 1966fas the last two entries of table 1 are chopped sine waves as is commonly created with thyristors such as scrs and triacs. figure 2a shows a typical circuit and figure 2b shows the resulting load voltage, switch voltage and load currents. the power delivered to the load depends on the firing angle, as well as any parasitic losses such as switch on voltage drop. real circuit waveforms will also typi- cally have significant ringing at the switching transition, dependent on exact circuit parasitics. for the purposes of this data sheet, scr waveforms refers to the ideal chopped sine wave, though the LTC1966 will do faithful rms-to-dc conversion with real scr waveforms as well. the case shown is for q = 90 , which corresponds to 50% of available power being delivered to the load. as noted in table 1, when q = 114 , only 25% of the available power is being delivered to the load and the power drops quickly as q approaches 180 . with an average rectification scheme and the typical calibration to compensate for errors with sine waves, the rms level of an input sine wave is properly reported; it is only with a non-sinusoidal waveform that errors occur. because of this calibration, and the output reading in v rms , the term true-rms got coined to denote the use of an actual rms-to-dc converter as opposed to a calibrated average rectifier. applicatio s i for atio wu uu rms-to-dc conversion definition of rms rms amplitude is the consistent, fair and standard way to measure and compare dynamic signals of all shapes and sizes. simply stated, the rms amplitude is the heating potential of a dynamic waveform. a 1v rms ac waveform will generate the same heat in a resistive load as will 1v dc. + r 1v dc r 1966 f01 same heat 1v ac rms r 1v (ac + dc) rms figure 1 mathematically, rms is the root of the mean of the square: vv rms = 2 alternatives to rms other ways to quantify dynamic waveforms include peak detection and average rectification. in both cases, an average (dc) value results, but the value is only accurate at the one chosen waveform type for which it is calibrated, typically sine waves. the errors with average rectification are shown in table 1. peak detection is worse in all cases and is rarely used. table 1. errors with average rectification vs true rms average rectified waveform v rms (v) error* square wave 1.000 1.000 11% sine wave 1.000 0.900 *calibrate for 0% error triangle wave 1.000 0.866 C3.8% scr at 1/2 power, 1.000 0.637 C29.3% q = 90 scr at 1/4 power, 1.000 0.536 C40.4% q = 114 control v load ac mains v line v thy 1966 f02a + + + i load v line q v load v thy i load 1966 f02b figure 2a figure 2b 11 LTC1966 sn1966 1966fas applicatio s i for atio wu uu how an rms-to-dc converter works monolithic rms-to-dc converters use an implicit com- putation to calculate the rms value of an input signal. the fundamental building block is an analog multiply/divide used as shown in figure 3. analysis of this topology is easy and starts by identifying the inputs and the output of the lowpass filter. the input to the lpf is the calculation from the multiplier/divider; (v in ) 2 /v out . the lowpass filter will take the average of this to create the output, mathematically: how the LTC1966 rms-to-dc converter works the LTC1966 uses a completely new topology for rms-to- dc conversion, in which a ds modulator acts as the divider, and a simple polarity switch is used as the multi- plier 1 as shown in figure 4. 1 multiple patents pending v v v v v v so v v v and vvor v v rms v out in out out in out out in out out in out in in = () ? ? ? ? ? () ? ? ? ? ? = () ? ? ? = () ? ? ? () = () = () = () 2 2 2 2 22 2 , , , , because v is dc, v out in figure 3. rms-to-dc converter with implicit computation v in v out 1966 f03 lpf v v in out () 2 unlike the prior generation rms-to-dc converters, the LTC1966 computation does not use log/antilog circuits, which have all the same problems, and more, of log/ antilog multipliers/dividers, i.e., linearity is poor, the band- width changes with the signal amplitude and the gain drifts with temperature. figure 4. topology of LTC1966 ? - s ref v in v out lpf 1 d v v in out a the ds modulator has a single-bit output whose average duty cycle (d) will be proportional to the ratio of the input signal divided by the output. the ds is a 2nd order modulator with excellent linearity. the single-bit output is used to selectively buffer or invert the input signal. again, this is a circuit with excellent linearity, because it operates at only two points: 1 gain; the average effective multipli- cation over time will be on the straight line between these two points. the combination of these two elements again creates a lowpass filter input signal equal to (v in ) 2 /v out , which, as shown above, results in rms-to-dc conversion. the lowpass filter performs the averaging of the rms function and must be a lower corner frequency than the lowest frequency of interest. for line frequency measure- ments, this filter is simply too large to implement on-chip, but the LTC1966 needs only one capacitor on the output to implement the lowpass filter. the user can select this capacitor depending on frequency range and settling time requirements, as will be covered in the design cookbook section to follow. this topology is inherently more stable and linear than log/ antilog implementations primarily because all of the signal processing occurs in circuits with high gain op amps operating closed loop. 12 LTC1966 sn1966 1966fas more detail of the LTC1966 inner workings is shown in the simplified schematic towards the end of this data sheet. note that the internal scalings are such that the ds output duty cycle is limited to 0% or 100% only when v in exceeds 4 ? v out . linearity of an rms-to-dc converter linearity may seem like an odd property for a device that implements a function that includes two very nonlinear processes: squaring and square rooting. however, an rms-to-dc converter has a transfer func- tion, rms volts in to dc volts out, that should ideally have a 1:1 transfer function. to the extent that the input to output transfer function does not lie on a straight line, the part is nonlinear. a more complete look at linearity uses the simple model shown in figure 5. here an ideal rms core is corrupted by both input circuitry and output circuitry that have imper- fect transfer functions. as noted, input offset is introduced in the input circuitry, while output offset is introduced in the output circuitry. any nonlinearity that occurs in the output circuity will corrupt the rms in to dc out transfer function. a nonlin- earity in the input circuitry will typically corrupt that transfer function far less simply because with an ac input, the rms-to-dc conversion will average the nonlinearity from a whole range of input values together. but the input nonlinearity will still cause problems in an rms-to-dc converter because it will corrupt the accuracy as the input signal shape changes. although an rms-to- dc converter will convert any input waveform to a dc output, the accuracy is not necessarily as good for all waveforms as it is with sine waves. a common way to describe dynamic signal wave shapes is crest factor. the crest factor is the ratio of the peak value relative to the rms value of a waveform. a signal with a crest factor of 4, for instance, has a peak that is four times its rms value. because this peak has energy (proportional to voltage squared) that is 16 times (4 2 ) the energy of the rms value, the peak is necessarily present for at most 6.25% (1/16) of the time. the LTC1966 performs very well with crest factors of 4 or less and will respond with reduced accuracy to signals with higher crest factors. the high performance with crest factors less than 4 is directly attributable to the high linearity throughout the LTC1966. applicatio s i for atio wu uu input circuitry ?v ios ?input nonlinearity ideal rms-to-dc converter output circuitry ?v oos ?output nonlinearity input output 1966 f05 figure 5. linearity model of an rms-to-dc converter 13 LTC1966 sn1966 1966fas applicatio s i for atio wu uu design cookbook the LTC1966 rms-to-dc converter makes it easy to implement a rather quirky function. for many applications all that will be needed is a single capacitor for averaging, appropriate selection of the i/o connections and power supply bypassing. of course, the LTC1966 also requires power. a wide variety of power supply configurations are shown in the typical applications section towards the end of this data sheet. capacitor value selection the rms or root-mean-squared value of a signal, the root of the mean of the square , cannot be computed without some averaging to obtain the mean function. the LTC1966 true rms-to-dc converter utilizes a single capacitor on the output to do the low frequency averaging required for rms-to-dc conversion. to give an accurate measure of a dynamic waveform, the averaging must take place over a sufficiently long interval to average, rather than track, the lowest frequency signals of interest. for a single averaging capacitor, the accuracy at low frequencies is depicted in figure 6. figure 6 depicts the so-called dc error that results at a given combination of input frequency and filter capacitor values 2 . it is appropriate for most applications, in which the output is fed to a circuit with an inherently band-limited frequency response, such as a dual slope/integrating a/d converter, a ds a/d converter or even a mechanical analog meter. figure 6. dc error vs input frequency c = 4.7 f input frequency (hz) 1 2.0 dc error (%) ?.6 ?.2 0.8 0.4 10 20 50 60 100 1966 f06 0 ?.8 ?.4 ?.0 0.6 0.2 c = 10 f c = 2.2 f c = 1.0 f c = 0.47 f c = 0.22 f c = 0.1 f figure 7. output ripple exceeds dc error time output 1966 f07 dc error (0.05%) ideal output dc average of actual output peak ripple (5%) actual output with ripple f = 2 f input peak error = dc error + peak ripple (5.05%) however, if the output is examined on an oscilloscope with a very low frequency input, the incomplete averaging will be seen, and this ripple will be larger than the error depicted in figure 6. such an output is depicted in figure 7. the ripple is at twice the frequency of the input because of the computation of the square of the input. the typical values shown, 5% peak ripple with 0.05% dc error, occur with c ave = 1 m f and f input = 10hz. if the application calls for the output of the LTC1966 to feed a sampling or nyquist a/d converter (or other circuitry that will not average out this double frequency ripple) a larger averaging capacitor can be used. this trade-off is depicted in figure 8. the peak ripple error can also be reduced by additional lowpass filtering after the LTC1966, but the simplest solution is to use a larger averaging capacitor. 2 this frequency-dependent error is in additon to the static errors that affect all readings and are therefore easy to trim or calibrate out. the error analyses section to follow discusses the effect of static error terms. 14 LTC1966 sn1966 1966fas a 1 m f capacitor is a good choice for many applications. the peak error at 50hz/60hz will be <1% and the dc error will be <0.1% with frequencies of 10hz or more. note that both figure 6 and figure 8 assume ac-coupled waveforms with a crest factor less than 2, such as sine waves or triangle waves. for higher crest factors and/or ac + dc waveforms, a larger c ave will generally be required. see crest factor and ac + dc waveforms. capacitor type selection the LTC1966 can operate with many types of capacitors. the various types offer a wide array of sizes, tolerances, parasitics, package styles and costs. ceramic chip capacitors offer low cost and small size, but are not recommended for critical applications. the value stability over voltage and temperature is poor with many types of ceramic dielectrics. this will not cause an rms- to-dc accuracy problem except at low frequencies, where it can aggravate the effects discussed in the previous section. if a ceramic capacitor is used, it may be neces- sary to use a much higher nominal value in order to assure the low frequency accuracy desired. another parasitic of ceramic capacitors is leakage, which is again dependent on voltage and particularly tempera- ture. if the leakage is a constant current leak, the i ? r drop of the leak multiplied by the output impedance of the LTC1966 will create a constant offset of the output voltage. if the leak is ohmic, the resistor divider formed with the LTC1966 output impedance will cause a gain error. for applicatio s i for atio wu uu < 0.1% gain accuracy degradation, the parallel impedance of the capacitor leakage will need to be >1000 times the LTC1966 output impedance. accuracy at this level can be hard to achieve with a ceramic capacitor, particularly with a large value of capacitance and at high temperature. for critical applications, a film capacitor, such as metal- ized polyester, will be a much better choice. although more expensive, and larger for a given value, the value stability and low leakage make metal-film capacitors a trouble-free choice. with any type of capacitor, the self-resonance of the capacitor can be an issue with the switched capacitor LTC1966. if the self-resonant frequency of the averaging capacitor is 1mhz or less, a second smaller capacitor should be added in parallel to reduce the impedance seen by the LTC1966 output stage at high frequencies. a capacitor 100 times smaller than the averaging capacitor will typically be small enough to be a low cost ceramic with a high quality dielectric such as x7r or npo/cog. input connections the LTC1966 input is differential and dc coupled. the LTC1966 responds to the rms value of the differential voltage between pin 2 and pin 3, including the dc portion of that difference. however, there is no dc-coupled path from the inputs to ground. therefore, at least one of the two inputs must be connected with a dc-return path to ground. both inputs must be connected to something. if either input is left floating, a zero volt output will result. figure 8. peak error vs input frequency with one cap averaging input frequency (hz) 1 2.0 peak error (%) ?.6 ?.2 0.8 0.4 10 20 50 60 100 1966 f08 0 ?.8 ?.4 ?.0 0.6 0.2 c = 100 f c = 47 f c = 22 f c = 10 f c = 4.7 f c = 2.2 f c = 1 f 15 LTC1966 sn1966 1966fas for single-ended dc-coupled applications, simply con- nect one of the two inputs (they are interchangeable) to the signal, and the other to ground. this will work well for dual supply configurations, but for single supply con- figurations it will only work well for unipolar input sig- nals. the LTC1966 input voltage range is from rail-to-rail, and when the input is driven above v dd or below v ss (ground for single supply operation) the gain and offset errors will increase substantially after just a few hundred millivolts of overdrive. fortunately, most single supply circuits measuring a dc-coupled rms value will include some reference voltage other than ground, and the second LTC1966 input can be connected to that point. for single-ended ac-coupled applications, figure 9 shows three alternate topologies. the first one, shown in figure 9a uses a coupling capacitor to one input while the other is grounded. this will remove the dc voltage difference from the input to the LTC1966, and it will therefore not be part of the resulting output voltage. again, this connection will work well with dual supply configurations, but in single supply configurations it will be necessary to raise the volt- age on the grounded input to assure that the signal at the active input stays within the range of v ss to v dd . if there is already a suitable voltage reference available, connect the second input to that point. if not, a midsupply voltage can be created with two resistors as shown in figure 9b. finally, if the input voltage is known to be between v ss and v dd , it can be ac coupled by using the configuration shown in figure 9c. whereas the dc return path was provided through pin 3 in figures 9a and 9b, in this case, the return path is provided on pin 2, through the input signal voltages. the switched capacitor action between the two input pins of the LTC1966 will cause the voltage on applicatio s i for atio wu uu the coupling capacitor connected to the second input to follow the dc average of the input voltage. for differential input applications, connect the two inputs to the differential signal. if ac coupling is desired, one of the two inputs can be connected through a series capacitor. in all of these connections, to choose the input coupling capacitor, c c , calculate the low frequency coupling time constant desired, and divide by the LTC1966 differential input impedance. because the LTC1966 input impedance is about 100 times its output impedance, this capacitor is typically much smaller than the output averaging capaci- tor. its requirements are also much less stringent, and a ceramic chip capacitor will usually suffice. output connections the LTC1966 output is differentially, but not symmetri- cally, generated. that is to say, the rms value that the LTC1966 computes will be generated on the output (pin 5) relative to the output return (pin 6), but these two pins are not interchangeable. for most applications, pin 6 will be tied to ground (pin 1), and this will result in the best accuracy. however, pin 6 can be tied to any voltage between v ss (pin 4) and v dd (pin 7) less the maximum output voltage swing desired. this last restriction keeps v out itself (pin 5) within the range of v ss to v dd . if a reference level other than ground is used, it should be a low impedance, both ac and dc, for proper operation of the LTC1966. use of a voltage in the range of v dd C 1v to v dd C 1.3v can lead to errors due to the switch dynamics as the nmos transistor is cut off. for this reason, it is recommended that out rtn = 0v if v dd is 3v. figure 9. single-ended ac-coupled input connection alternatives + LTC1966 v dd v dd v ss v dd v ss or gnd (9a) c c in1 v in in2 2 3 LTC1966 (9b) c c r1 100k r2 100k in1 v in v dd in2 2 3 LTC1966 (9c) c c in1 v in 1966 f07 v dc in2 2 3 16 LTC1966 sn1966 1966fas in any configuration, the averaging capacitor should be connected between pins 5 and 6. the LTC1966 rms-dc output will be a positive voltage created at v out (pin 5) with respect to out rtn (pin 6). power supply bypassing the LTC1966 is a switched capacitor device, and large transient power supply currents will be drawn as the switching occurs. for reliable operation, standard power supply bypassing must be included. for single supply operation, a 0.01 m f capacitor from v dd (pin 7) to gnd (pin 1) located close to the device will suffice. for dual supplies, add a second 0.01 m f capacitor from v ss (pin 4) to gnd (pin 1), located close to the device. if there is a good quality ground plane available, the capacitors can go directly to that instead. power supply bypass capacitors can, of course, be inexpensive ceramic types. the LTC1966 needs at least 2.7v for its power supply, more for dual supply configurations. the range of allow- able negative supply voltages (v ss ) vs positive supply voltages (v dd ) is shown in figure 10. mathematically, the v ss constraint is: C 3 ? (v dd C 2.7v) v ss gnd the LTC1966 has internal esd absorption devices, which are referenced to the v dd and v ss supplies. for effective in-circuit esd immunity, the v dd and v ss pins must be connected to a low external impedance. this can be accomplished with low impedance power planes or simply with the recommended 0.01 m f decoupling to ground on each supply. up and running! if you have followed along this far, you should have the LTC1966 up and running by now! dont forget to enable the device by grounding pin 8, or driving it with a logic low. keep in mind that the LTC1966 output impedance is fairly high, and that even the standard 10m w input impedance of a digital multimeter (dmm) or a 10 scope probe will load down the output enough to degrade its typical gain error of 0.1%. in the end application circuit, either a buffer or another component with an extremely high input imped- ance (such as a dual slope integrating adc) should be used. for laboratory evaluation, it may suffice to use a bench-top dmm with the ability to disconnect the 10m w shunt. if you are still having trouble, it may be helpful to skip ahead a few pages and review the troubleshooting guide. what about response time? with a large value averaging capacitor, the LTC1966 can easily perform rms-to-dc conversion on low frequency signals. it compares quite favorably in this regard to prior- generation products because nothing about the ds circuitry is temperature sensitive. so the rms result doesnt get distorted by signal driven thermal fluctuations like a log-antilog circuit output does. however, using large value capacitors results in a slow response time. figure 11 shows the rising and falling step responses with a 1 m f averaging capacitor. although they both appear at first glance to be standard exponential- decay type settling, they are not. this is due to the nonlinear nature of an rms-to-dc calculation. also note the change in the time scale between the two; the rising edge is more than twice as fast to settle to a given accuracy. again this is a necessary consequence of rms- to-dc calculation. 3 although shown with a step change between 0mv and 100mv, the same response shapes will occur with the LTC1966 for any step size. this is in marked contrast to applicatio s i for atio wu uu 3 to convince oneself of this necessity, consider a pulse train of 50% duty cycle between 0mv and 100mv. at very low frequencies, the LTC1966 will essentially track the input. but as the input frequency is increased, the average result will converge to the rms value of the input. if the rise and fall characteristics were symmetrical, the output would converge to 50mv. in fact though, the rms value of a 100mv dc-coupled 50% duty cycle pulse train is 70.71mv, which the asymmetrical rise and fall characteristics will converge to as the input frequency is increased. figure 10. v ss limits vs v dd v dd (v) 2.5 ? v ss (v) ? ? ? ? 0 3 3.5 4 4.5 1966 f10 5 5.5 ? LTC1966 operates in this range 17 LTC1966 sn1966 1966fas prior generation log/antilog rms-to-dc converters, whose averaging time constants are dependent on the signal level, resulting in excruciatingly long waits for the output to go to zero. the shape of the rising and falling edges will be dependent on the total percent change in the step, but for less than the 100% changes shown in figure 11, the responses will be less distorted and more like a standard exponential decay. for example, when the input amplitude is changed from 100mv to 110mv (+10%) and back (C10%), the step responses are essentially the same as a standard expo- nential rise and decay between those two levels. in such cases, the time constant of the decay will be in between that of the rising edge and falling edge cases of figure 11. therefore, the worst case is the falling edge response as it goes to zero, and it can be used as a design guide. applicatio s i for atio wu uu figure 12 shows the settling accuracy vs settling time for a variety of averaging capacitor values. if the capacitor value previously selected (based on error requirements) gives an acceptable settling time, your design is done. but with 100 m f, the settling time to even 10% is a full 38 seconds, which is a long time to wait. what can be done about such a design? if the reason for choosing 100 m f is to keep the dc error with a 75mhz input less than 0.1%, the answer is: not much. the settling time to 1% of 76 seconds is just 5.7 cycles of this extremely low frequency. averaging very low frequency signals takes a long time. however, if the reason for choosing 100 m f is to keep the peak error with a 10hz input less than 0.05%, there is another way to achieve that result with a much improved settling time. figure 11a. LTC1966 rising edge with c ave = 1 m f figure 11b. LTC1966 falling edge with c ave = 1 m f time (sec) 0 0 LTC1966 output (mv) 20 40 60 80 100 120 0.1 0.2 0.3 0.4 1966 f11a 0.5 c ave = 1 f time (sec) 0 0 LTC1966 output (mv) 20 40 60 80 100 120 0.2 0.4 0.6 0.8 1966 f11b 1 c ave = 1 f settling time (sec) 0.01 0.1 settling accuracy (%) 1 10 110 0.1 100 1966 f12 c = 100 f c = 47 f c = 22 f c = 10 f c = 4.7 f c = 2.2 f c = 0.47 f c = 0.22 f c = 0.1 f c = 1 f figure 12. LTC1966 settling time with one cap averaging 18 LTC1966 sn1966 1966fas applicatio s i for atio wu uu reducing ripple with a post filter the output ripple is always much larger than the dc error, so filtering out the ripple can reduce the peak error substantially, without the large settling time penalty of simply increasing the averaging capacitor. figure 13 shows a basic 2nd order post filter, for a net 3rd order filtering of the LTC1966 rms calculation. it uses the 85k w output impedance of the LTC1966 as the first resis- tor of a 3rd order sallen-key active-rc filter. this topology features a buffered output, which can be desirable de- pending on the application. however, there are disadvan- tages to this topology, the first of which is that the op amp input voltage and current errors directly degrade the effec- tive LTC1966 v oos . the table inset in figure 13 shows these errors for four of linear technologys op amps. a second disadvantage is that the op amp output has to operate over the same range as the LTC1966 output, includ- ing ground, which in single supply applications is the nega- tive supply. although the LTC1966 output will function fine just millivolts from the rail, most op amp output stages (and even some input stages) will not. there are at least two ways to address this. first of all, the op amp can be operated split supply if a negative supply is available. just the op amp would need to do so; the LTC1966 can remain single sup- ply. a second way to address this issue is to create a signal reference voltage a half volt or so above ground. this is most attractive when the circuitry that follows has a differential input, so that the tolerance of the signal reference is not a concern. to do this, tie all three ground symbols shown in figure 13 to the signal reference, as well as to the differ- ential return for the circuitry that follows. figure 14 shows an alternative 2nd order post filter, for a net 3rd order filtering of the LTC1966 rms calculation. it also uses the 85k w output impedance of the LTC1966 as the first resistor of a 3rd order active-rc filter, but this topology filters without buffering so that the op amp dc error characteristics do not affect the output. although the output impedance of the LTC1966 is increased from 85k w to 285k w , this is not an issue with an extremely high input impedance load, such as a dual-slope integrating adc like the icl7106. and it allows a generic op amp to be used, such as the sot-23 one shown. furthermore, it easily works on a single supply rail by tying the noninverting input of the op amp to a low noise reference as optionally shown. this reference will not change the dc voltage at the circuit output, although it does become the ac ground for the filter, thus the (relatively) low noise requirement. step responses with a post filter b oth of the post filters, shown in figures 13 and 14, are optimized for additional filtering with clean step re- sponses. the 85k w output impedance of the LTC1966 working into a 1 m f capacitor forms a 1st order lpf with a C3db frequency of ~1.8hz. the two filters have 1 m f at the LTC1966 output for easy comparison with a 1 m f-only case, and both have the same relative bessel-like shape. however, because of the topological differences of pole placements between the various components within the two filters, the net effective bandwidth for figure 13 is slightly higher ( ? 1.2 ? 1.8 ? 2.1hz) than with 1 m f alone, while the bandwidth for figure 14 is somewhat lower figure 14. dc accurate post filter LTC1966 c ave 1 f 5 6 other ref voltage, see text r1 200k + r2 681k c1 0.22 f c2 0.22 f lt1782 1066 f14 figure 13. buffered post filter LTC1966 c ave 1 f 5 6 r1 38.3k + r2 169k r b c2 0.1 f c1 1 f lt1880 1966 f13 op amp LTC1966 v oos v ios i b/os ?r total offset r b value i sq lt1494 375 v 73 v 648 v 294k 1 a lt1880 150 v 329 v 679 v short 1.2ma lt1077 60 v 329 v 589 v 294k 48 a lt2050 3 v 27 v 230 v short 750 a 200 v 19 LTC1966 sn1966 1966fas applicatio s i for atio wu uu ( ? 0.7 ? 1.8 ? 1.3hz) than with 1 m f alone. to adjust the bandwidth of either of them, simply scale all the capaci- tors by a common multiple, and leave the resistors unchanged. the step responses of the LTC1966 with 1 m f-only and with the two post filters are shown in figure 15. this is the rising edge rms output response to a 10hz input starting at t = 0. although the falling edge response is the worst case for settling, the rising edge illustrates the ripple that these post filters are designed to address, so the rising edge makes for a better intuitive comparison. the initial rise of the LTC1966 will have enhanced slew rates with dc and very low frequency inputs due to saturation effects in the ds modulator. this is seen in figure 15 in two ways. first, the 1 m f-only output is seen to rise very quickly in the first 40ms. the second way this effect shows up is that the post filter outputs have a modest overshoot, on the order of 3mv to 4mv, or 3% to 4%. this is only an issue with input frequency bursts at 50hz or less, and even with the overshoot, the settling to a given level of accuracy improves due to the initial speedup. as predicted by figure 6, the dc error with 1 m f is well under 1mv and is not noticeable at this scale. however, as predicted by figure 8, the peak error with the ripple from a 10hz input is much larger, in this case about 5mv. as can be clearly seen, the post filters reduce this ripple. even the wider bandwidth of figure 13s filter is seen to cut the ripple down substantially (to < 1mv) while the settling to 1% happens faster. with the narrower bandwidth of figure 14s filter, the step response is somewhat slower, but the double frequency output ripple is just 180 m v. figure 16 shows the step response of the same three cases with a burst of 60hz rather than 10hz. with 60hz, the initial portion of the step response is free of the boost seen in figure 15 and the two post-filter responses have less than 1% overshoot. the 1 m f-only case still has noticeable 120hz ripple, but both filters have removed all detectable ripple on this scale. this is to be expected; the first order filter will reduce the ripple about 6:1 for a 6:1 change in frequency, while the third order filters will reduce the ripple about 6 3 :1 or 216:1 for a 6:1 change in frequency. again, the two filter topologies have the same relative shape, so the step response and ripple filtering trade-offs of the two are the same, with the same performance of each possible with the other by scaling it accordingly. figures 17 and 18 show the peak error vs. frequency for a selection of capacitors for the two different filter topolo- gies. to keep the clean step response, scale all three capacitors within the filter. scaling the buffered topology of figure 13 is simple because the capacitors are in a 10:1:10 ratio. scaling the dc accurate topology of figure 14 can be done with standard value capacitors; one decade of scaling is shown in table 2. table 2: one decade of capacitor scaling for figure 14 with eia standard values c ave c 1 = c 2 = 1 m f 0.22 m f 1.5 m f 0.33 m f 2.2 m f 0.47 m f 3.3 m f 0.68 m f 4.7 m f1 m f 6.8 m f1.5 m f figure 16. step responses with 60hz burst figure 15. step responses with 10hz burst input burst 200mv/ div 20mv/ div 0 0 1 f only figure 13 figure 14 step response 100ms/div 1966 f15 input burst 200mv/ div 20mv/ div 0 0 1 f only figure 13 figure 14 step response 100ms/div 1966 f16 20 LTC1966 sn1966 1966fas applicatio s i for atio wu uu figures 19 and 20 show the settling time versus settling accuracy for the buffered and dc accurate post filters, respectively. the different curves represent different scalings of the filters, as indicated by the c ave value. these are comparable to the curves in figure 12 (single capacitor case), with somewhat less settling time for the buffered post filter, and somewhat more settling time for the dc-accurate post filter. these differences are due to the change in overall bandwidth as mentioned earlier. the other difference is the settling behavior of the filters below the 1% level. unlike the case of a 1st order filter, any 3rd order filter can have overshoot and ringing. the filter designs presented here have minimal overshoot and ringing, but are somewhat sensitive to component mis- matches. even the 12% tolerance of the LTC1966 output impedance can be enough to cause some ringing. the dashed lines indicate what can happen when 5% capaci- tors and 1% resistors are used. although the settling times for the post-filtered configura- tions shown on figures 19 and 20 are not that much different from those with a single capacitor, the point of using a post filter is that the settling times are far better for a given level peak error. the filters dramatically reduce the low frequency averaging ripple with far less impact on settling time. crest factor and ac + dc waveforms in the preceding discussion, the waveform was assumed to be ac coupled, with a modest crest factor. both assumptions ease the requirements for the averaging capacitor. with an ac-coupled sine wave, the calculation engine squares the input, so the averaging filter that follows is required to filter twice the input frequency, making its job easier. but with a sinewave that includes dc offset, the square of the input has frequency content at the input frequency and the filter must average out that lower input frequency (hz) 1 2.0 peak error (%) ?.6 ?.2 0.8 0.4 10 100 1966 f18 0 ?.8 ?.4 ?.0 0.6 0.2 c = 10 f c = 4.7 f c = 2.2 f c = 1.0 f c = 0.47 f c = 0.22 f c = 0.1 f figure 18. peak error vs input frequency with dc-accurate post filter input frequency (hz) 1 2.0 peak error (%) ?.6 ?.2 0.8 0.4 10 100 1966 f17 0 ?.8 ?.4 ?.0 0.6 0.2 c = 10 f c = 4.7 f c = 2.2 f c = 1.0 f c = 0.47 f c = 0.22 f c = 0.1 f figure 17. peak error vs input frequency with buffered post filter 21 LTC1966 sn1966 1966fas frequency. so with ac + dc waveforms, the required value for c ave should be based on half of the lowest input frequency, using the same design curves presented in figures 6, 8, 17 and 18. crest factor, which is the peak to rms ratio of a dynamic signal, also effects the required c ave value. with a higher crest factor, more of the energy in the signal is concentrated into a smaller portion of the waveform, and the averaging has to ride out the long lull in signal activity. for busy waveforms, such as a sum of sine waves, ecg traces or scr-chopped sine waves, the required value for c ave should be based on the lowest fundamental input frequency divided as such: f f cf design input min = () 32 applicatio s i for atio wu uu using the same design curves presented in figures 6, 8, 17 and 18. for the worst case of square top pulse trains, that are always either zero volts or the peak voltage, base the selection on the lowest fundamental input frequency divided by twice as much: f f cf design input min = () 62 the effects of crest factor and dc offsets are cumulative. so for example, a 10% duty cycle pulse train from 0v peak to 1v peak (cf = ? 10 = 3.16) repeating at 16.67ms (60hz) input is effectively only 30hz due to the dc asymmetry and is effectively only: fhz design == 30 6 3 16 2 378 . . for the purposes of figures 6, 8, 17 and 18. figure 20. settling time with dc-accurate post filter figure 19. settling time with buffered post filter settling time (sec) 0.01 0.1 settling accuracy (%) 1 10 1 0.1 10 100 1066 f14 c = 100 f c = 47 f c = 22 f c = 10 f c = 4.7 f c = 2.2 f c = 1.0 f c = 0.47 f c = 0.22 f c = 0.1 f settling time (sec) 0.01 0.1 settling accuracy (%) 1 10 1 0.1 10 100 1066 f20 c = 100 f c = 47 f c = 22 f c = 10 f c = 4.7 f c = 2.2 f c = 1.0 f c = 0.47 f c = 0.22 f c = 0.1 f 22 LTC1966 sn1966 1966fas obviously, the effect of crest factor is somewhat simplified above given the factor of two difference based on a subjective description of the waveform type. the results will vary somewhat based on actual crest factor and waveform dynamics and the type of filtering used. the above method is conservative for some cases and about right for others. the LTC1966 works well with signals whose crest factor is 4 or less. at higher crest factors, the internal ds modulator will saturate, and results will vary depending on the exact frequency, shape and (to a lesser extent) ampli- tude of the input waveform. the output voltage could be higher or lower than the actual rms of the input signal. the ds modulator may also saturate when signals with crest factors less than 4 are used with insufficient averag- ing. this will only occur when the output droops to less than 1/4 of the input voltage peak. for instance, a dc- coupled pulse train with a crest factor of 4 has a duty cycle of 6.25% and a 1v peak input is 250mv rms . if this input is 50hz, repeating every 20ms, and c ave = 1 m f, the output will droop during the inactive 93.75% of the waveform. this droop is calculated as: v v e min rms inactive time = ? ? ? ? ? - ? ? ? ? 2 1 2 z c out ave for the LTC1966, whose output impedance (z out ) is 85k w , this droop works out to C 5.22%, so the output would be reduced to 237mv at the end of the inactive portion of the input. when the input signal again climbs to 1v peak , the peak/output ratio is 4.22. with c ave = 10 m f, the droop is only C 0.548% to 248.6mv and the peak/output ratio is just 4.022, which the LTC1966 has enough margin to handle without error. for crest factors less than 3.5, the selection of c ave as previously described should be sufficient to avoid this droop and modulator saturation effect. but with crest factors above 3.5, the droop should also be checked for each design. error analyses once the rms-to-dc conversion circuit is working, it is time to take a step back and do an analysis of the accuracy applicatio s i for atio wu uu of that conversion. the LTC1966 specifications include three basic static error terms, v oos , v ios and gain. the output offset is an error that simply adds to (or subtracts from) the voltage at the output. the conversion gain of the LTC1966 is nominally 1.000 v dcout /v rmsin and the gain error reflects the extent to which this conversion gain is not perfectly unity. both of these affect the results in a fairly obvious way. input offset on the other hand, despite its conceptual simplicity, effects the output in a nonobvious way. as its name implies, it is a constant error voltage that adds directly with the input. and it is the sum of the input and v ios that is rms converted. this means that the effect of v ios is warped by the nonlinear rms conversion. with 0.2mv (typ) v ios , and a 200mv rms ac input, the rms calculation will add the dc and ac terms in an rms fashion and the effect is negligible: v out = ? (200mv ac) 2 + (0.2mv dc) 2 = 200.0001mv = 200mv + 1/2ppm but with 10 less ac input, the error caused by v ios is 100 larger: v out = ? (20mv ac) 2 + (0.2mv dc) 2 = 20.001mv = 20mv + 50ppm this phenomena, although small, is one source of the LTC1966s residual nonlinearity. on the other hand, if the input is dc coupled, the input offset voltage adds directly. with +200mv and a +0.2mv v ios , a 200.2mv output will result, an error of 0.1% or 1000ppm. with dc inputs, the error caused by v ios can be positive or negative depending if the two have the same or opposing polarity. the total conversion error with a sine wave input using the typical values of the LTC1966 static errors is computed as follows: v out = ( ? (500mv ac) 2 + (0.2mv dc) 2 ) ? 1.001 + 0.1mv = 500.600mv = 500mv + 0.120% 23 LTC1966 sn1966 1966fas in1 v dd v dd v ss v ss r sw (typ) 6k c eq 2.5pf (typ) c eq 2.5pf (typ) i in1 in2 i in2 1966 f21 r sw (typ) 6k iin vv r iin vv r rm avg in in eq avg in in eq eq 1 2 8 12 21 () = - () = - = w applicatio s i for atio wu uu v out = ( ? (50mv ac) 2 + (0.2mv dc) 2 ) ? 1.001 + 0.1mv = 50.150mv = 50mv + 0.301% v out = ( ? (5mv ac) 2 + (0.2mv dc) 2 ) ? 1.001 + 0.1mv = 5.109mv = 5mv + 2.18% as can be seen, the gain term dominates with large inputs, while the offset terms become significant with smaller inputs. in fact, 5mv is the minimum rms level needed to keep the LTC1966 calculation core functioning normally, so this represents the worst-case of usable input levels. using the worst-case values of the LTC1966 static errors, the total conversion error is: v out = ( ? (500mv ac) 2 + (0.8mv dc) 2 ) ? 1.003 + 0.2mv = 501.70mv = 500mv + 0.340% v out = ( ? (50mv ac) 2 + (0.8mv dc) 2 ) ? 1.003 + 0.2mv = 50.356mv = 50mv + 0.713% v out = ( ? (5mv ac) 2 + (0.8mv dc) 2 ) ? 1.003 + 0.2mv = 5.279mv = 5mv + 5.57% these static error terms are in addition to dynamic error terms that depend on the input signal. see the design cookbook for a discussion of the dc conversion error with low frequency ac inputs. the LTC1966 bandwidth limita- tions cause additional errors with high frequency inputs. another dynamic error is due to crest factor. the LTC1966 performance versus crest factor is shown in the typical performance characteristics. output errors versus frequency as mentioned in the design cookbook, the LTC1966 per- forms very well with low frequency and very low frequency inputs, provided a large enough averaging capacitor is used. however, the LTC1966 will have additional dynamic errors as the input frequency is increased. the LTC1966 is de- signed for high accuracy rms-to-dc conversion of sig- nals into the audible range. the input sampling amplifiers have a C 3db frequency of 800khz or so. however, the switched capacitor circuitry samples the inputs at a mod- est 100khz nominal. the response versus frequency is depicted in the typical performance characteristics titled input signal bandwidth. although there is a pattern to the response versus frequency that repeats every sample fre- quency, the errors are not overwhelming. this is because LTC1966 rms calculation is inherently wideband, operat- ing properly with minimal oversampling, or even undersampling, using several proprietary techniques to exploit the fact that the rms value of an aliased signal is the same as the rms value of the original signal. however, a fundamental feature of the ds modulator is that sample estimation noise is shaped such that minimal noise occurs with input frequencies much less than the sampling fre- quency, but such noise peaks when input frequency reaches half the sampling frequency. fortunately the LTC1966 output averaging filter greatly reduces this error, but the rms-to-dc topology frequency shifts the noise to low (baseband) frequencies. so with input frequencies above 5khz to 10khz, the output will slowly wander around a few percent. input impedance the LTC1966 true rms-to-dc converter utilizes a 2.5pf capacitor to sample the input at a nominal 100khz sample frequency. this accounts for the 8m w input impedance. see figure 21 for the equivalent analog input circuit. note however, that the 8m w input impedance does not directly affect the input sampling accuracy. for instance, if a 100k source resistance is used to drive the LTC1966, the sampling action of the input stage will drag down the voltage seen at the input pins with small spikes at every sample clock edge as the sample capacitor is connected to be charged. the time constant of this combination is figure 21. LTC1966 equivalent analog input circuit 24 LTC1966 sn1966 1966fas small, 2.5pf ? 100k w = 250ns, and during the 2.5 m s period devoted to sampling, ten time constants elapse. this allows each sample to settle to within 46ppm and it is these samples that are used to compute the rms value. this is a much higher accuracy than the LTC1966 conver- sion limits, and far better than the accuracy computed via the simplistic resistive divider model: vv r rr v m mk v in source in in source source source = + = w w+ w = 8 8 100 125 ? % this resistive divider calculation does give the correct model of what voltage is seen at the input terminals by a parallel load averaged over a several clock cycles, which is what a large shunt capacitor will doaverage the current spikes over several clock cycles. when high source impedances are used, care must be taken to minimize shunt capacitance at the LTC1966 input so as not to increase the settling time. shunt capacitance of just 2.5pf will double the input settling time constant and the error in the above example grows from 46ppm to 0.67% (6700ppm). a 13pf scope probe will increase the error to almost 20%. as a consequence, it is important to not try to filter the input with large input capacitances unless driven by a low impedance. keep time constant << 2.5 m s. when the LTC1966 is driven by op amp outputs, whose low dc impedance can be compromised by sharp capaci- tive load switching, a small series resistor may be added. a 10k resistor will easily settle with the 2.5pf input sampling capacitor to within 1ppm. these are important points to consider both during design and debug. during lab debug, and even production testing, a high value series resistor to any test point is advisable. output impedance the LTC1966 output impedance during operation is simi- larly due to a switched capacitor action. in this case, 59pf of on-chip capacitance operating at 100khz translates into 170k w . the closed-loop rms-to-dc calculation cuts that in half to the nominal 85k w specified. in order to create a dc result, a large averaging capacitor is required. capacitive loading and time constants are not an issue on the output. however, resistive loading is an issue and the 10m w impedance of a dmm or 10 scope probe will drag the output down by C0.85% typ. during shutdown, the switching action is halted and a fixed 30k resistor shunts v out to out rtn so that c ave is discharged. interfacing with an adc the LTC1966 output impedance and the rms averaging ripple need to be considered when using an analog-to- digital converter (adc) to digitize the LTC1966 rms result. the simplest configuration is to connect the LTC1966 directly to the input of a type 7106/7136 adc as shown in figure 22a. these devices are designed specifically for dvm/dpm use and include display drivers for a 3 1/2 digit lcd segmented display. using a dual-slope conversion, the input is sampled over a long integration window, which results in rejection of line frequency ripple when integra- tion time is an integer number of line cycles. finally, these parts have an input impedance in the g w range, with specified input leakage of 10pa to 20pa. such a leakage, combined with the LTC1966 output impedance, results in just 1 m v to 2 m v of additional output offset voltage. another type of adc that has inherent rejection of rms averaging ripple is an oversampling ds adc such as the ltc2420. its input impedance is 6.5m w , but only when it is sampling. since this occurs only half the time at most, if it directly loads the LTC1966, a gain error of C 0.54% to C 0.73% results. in fact, the ltc2420 dc input current is not zero at 0v, but rather at one half its reference, so both applicatio s i for atio wu uu 25 LTC1966 sn1966 1966fas an output offset and a gain error will result. these errors will vary from part to part, but with a specific LTC1966 and ltc2420 combination, the errors will be fixed, varying less than 0.05% over temperature. so a system that has digital calibration can be quite accurate despite the nomi- nal gain and offset error. with 20 bits of resolution, this part is more accurate than the LTC1966, but the extra resolution is helpful because it reduces nonlinearity at the lsb transitions as a digital gain correction is made. furthermore, its small size and ease of use make it attractive. this connection is shown in figure 22b, where the ltc2420 is set to continuously convert by grounding the cs pin. the gain error will be less if cs is driven at a slower rate, however, the rate should either be consistent or at a rate low enough that the LTC1966 and its output capacitor have fully settled by the beginning of each conversion, so that the loading errors are consistent. the low power consumption of the LTC1966 makes it well- suited for battery-powered applications, and its slow output (dc) makes it an ideal candidate for a micropower adc. figure 10 in application note 75, for instance, details a 10-bit adc with a 35ms conversion time that uses just 29 m a of supply current. such an adc may also be of use within a 4ma to 20ma loop. other types of adcs sample the input signal once and perform a conversion on that one sample. with these adcs (nyquist adcs), a post filter will be needed in most cases to reduce the peak error with low input frequencies. the dc-accurate filter of figure 14 is attractive from an error standpoint, but it increases the impedance at the adc input. in most cases, the buffered post filter of figure 13 will be more appropriate for use with nyquist analog-to-digital converters. system calibration the LTC1966 static accuracy can be improved with end- system calibration. traditionally, calibration has been done at the factory, or at a service depot only, typically using manually adjusted potentiometers. increasingly, systems are being designed for electronic calibration where the accuracy corrections are implemented in digital code wherever possible, and with calibration dacs where necessary. additionally, many systems are now designed for self calibration, in which the calibration occurs inside the machine, automatically without user intervention. whatever calibration scheme is used, the linearity of the LTC1966 will improve the calibrated accuracy over that achievable with older log/antilog rms-to-dc converters. additionally, calibration using dc reference voltages are essentially as accurate with the LTC1966 as those using ac reference voltages. older log/antilog rms-to-dc con- verters required nonlinear input stages (rectifiers) whose linearity would typically render dc-based calibration unworkable. the following are four suggested calibration methods. implementations of the suggested adjustments are de- pendent on the system design, but in many cases, gain and output offset can be corrected in the digital domain, and will include the effect of all gains and offsets from the LTC1966 output through the adc. input offset voltage, on the other hand, will have to be corrected with adjustment to the actual analog input to the LTC1966. ac-only, 1 point the dominant error at full scale will be caused by the gain error, and by applying a full-scale sine wave input, this error can be measured and corrected for. unlike older log/ antilog rms-to-dc converters, the correction should be made for zero error at full scale to minimize errors through out the dynamic range. applicatio s i for atio wu uu c ave LTC1966 output out rtn 7106 type in hi in lo 5 6 31 1966 f22a 30 c ave LTC1966 output out rtn ltc2420 v in serial data digitally correct loading errors gnd sdo sck cs 5 6 3 1966 f22b 4 figure 22a. interfacing to dvm/dpm adc figure 22b. interfacing to ltc2420 26 LTC1966 sn1966 1966fas applicatio s i for atio wu uu the best frequency for the calibration signal is roughly ten times the C 0.1% dc error frequency. for 1 m f, C 0.1% dc error occurs at 8hz, so 80hz is a good calibration frequency, although anywhere from 60hz to 100hz should suffice. the trade-off here is that on the one hand, the dc error is input frequency dependent, so a calibration signal fre- quency high enough to make the dc error negligible should be used. on the other hand, as low a frequency as can be used is best to avoid attenuation of the calibrated ac signal, either from parasitic rc loading or insufficient op amp gain. for instance, with a 1khz calibration signal, a 1mhz op amp will typically only have 60db of open-loop gain, so it could attenuate the calibration signal a full 0.1%. ac-only, 2 point the next most significant error for ac-coupled applica- tions will be the effect of output offset voltage, noticeable at the bottom end of the input scale. this too can be calibrated out if two measurements are made, one with a full-scale sine wave input and a second with a sine wave input (of the same frequency) at 10% of full scale. the trade-off in selecting this second level is that it should be small enough that the gain error effect becomes small compared to the gain error effect at full scale, while on the other hand, not using so small an input that the input offset voltage becomes an issue. the calculations of the error terms for a 200mv full-scale case are: gain = reading at 200mv reading at 20mv 180mv output offset = reading at 20mv gain 20mv dc, 2 point dc-based calibration is preferable in many cases because a dc voltage of known, good accuracy is easier to generate than such an ac calibration voltage. the only down side is that the LTC1966 input offset voltage plays a role. it is therefore suggested that a dc-based calibration scheme check at least two points: full scale. applying the Cfull- scale input can be done by physically inverting the voltage or by applying the same +full-scale input to the opposite LTC1966 input. for an otherwise ac-coupled application, only the gain term may be worth correcting for, but for dc-coupled applications, the input offset voltage can also be calcu- lated and corrected for. the calculations of the error terms for a 200mv full-scale case are: gain = reading at 200mv + reading at 200mv 400mv input offset = reading at 200mv reading at 200mv 2 gain note: calculation of and correction for input offset voltage are the only way in which the two LTC1966 inputs (in1, in2) are distinguishable from each other. the calculation above assumes the standard definition of offset; that a positive offset is the case of a positive voltage error inside the device that must be corrected by applying a like negative voltage outside. the offset is referred to which- ever pin is driven positive for the +full-scale reading. dc, 3 point one more point is needed with a dc calibration scheme to determine output offset voltage: +10% of full scale. the calculation of the input offset is the same as for the 2-point calibration above, while the gain and output offset are calculated for a 200mv full-scale case as: gain = reading at 200mv reading at 20mv 180mv output offset = reading at 200mv +reading at 200mv 400mv gain 2 27 LTC1966 sn1966 1966fas troubleshooting guide top ten LTC1966 application mistakes 1. circuit wont workCdead on arrivalCno power drawn. C probably forgot to enable the LTC1966 by pulling pin 8 low. solution: tie pin 8 to pin 1. 2. circuit wont work, but draws power. zero or very little output, single-ended input application. C probably didnt connect both input pins. solution: tie both inputs to something. see input connections in the design cookbook. 4. gain is low by a few percent, along with other screwy results. C probably tried to use output in a floating, differential manner. solution: tie pin 6 to a low impedance. see output connections in the design cookbook. type 7136 adc LTC1966 hi 31 30 5 6 lo v out out rtn 1966 ts04 ground pin 6 5. offsets perceived to be out of specification because 0v in 1 0v out. C the offsets are not specified at 0v in. no rms-to- dc converter works well at 0 due to a divide-by-zero calculation. solution: measure v ios /v oos by extrapolating read- ings > 5mv dc . 6. linearity perceived to be out of specification particu- larly with small input signals. C this could again be due to using 0v in as one of the measurement points. solution: check linearity from 5mv rms to 500mv rms . C the input offset voltage can cause small ac linear ityerrors at low input amplitudes as well. see error analyses section. possible solution: include a trim for input offset. applicatio s i for atio wu uu 3. screwy results, particularly with respect to linearity or high crest factors; differential input application. C probably ac-coupled both input pins. solution: make at least one input dc-coupled. see input connections in the design cookbook. LTC1966 connect pin 3 in1 2 3 nc in2 1966 ts02 LTC1966 in1 2 3 in2 1966 ts03 dc-couple one input LTC1966 dc-connect one input in1 2 3 in2 28 LTC1966 sn1966 1966fas 7. output is noisy with >10khz inputs. C this is a fundamental characteristic of this topol- ogy. the LTC1966 is designed to work very well with inputs of 1khz or less. it works okay as high as 1mhz, but it is limited by aliased ds noise. solution: bandwidth limit the input or digitally filter the resulting output. 8. large errors occur at crest factors approaching, but less than 4. C insufficient averaging. solution: increase c ave . see crest factor and ac + dc waveforms section for discussion of output droop. 9. screwy results, errors > spec limits, typically 1% to 5%. C high impedance (85k w ) and high accuracy (0.1%) require clean boards! flux residue, finger grime, etc. all wreak havoc at this level. solution: wash the board. LTC1966 keep board clean 10. gain is low by @ 1% or more, no other problems. C probably due to circuit loading. with a dmm or a 10 scope probe, z in = 10m w . the LTC1966 output is 85k w , resulting in C 0.85% gain error. output impedance is higher with the dc accurate post filter. solution: remove the shunt loading or buffer the output. C loading can also be caused by cheap averaging capacitors. solution: use a high quality metal film capacitor for c ave . 200mv rms in ?.85% dmm dcv LTC1966 10m 5 85k 6 v out out rtn 1966 ts10 loading drags down gain mv applicatio s i for atio wu uu 29 LTC1966 sn1966 1966fas typical applicatio s u 5v supplies, differential, dc-coupled rms-to-dc converter v dd 5v ?v LTC1966 in1 dc output c ave 1 f in2 1966 ta03 v out dc + ac inputs (1v peak differential) out rtn gnd en v ss 2.7v single supply, single ended, ac-coupled rms-to-dc converter with shutdown v dd 2.7v 2.7v/3v cmos LTC1966 in1 dc output c ave 1 f c c 0.1 f in2 1966 ta04 v out ac input (1v peak ) out rtn gnd en v ss off on 5v single supply, differential, ac-coupled rms-to-dc converter v dd 5v LTC1966 in1 dc output c ave 1 f c c 0.1 f in2 1966 ta05 v out ac inputs (1v peak differential) out rtn gnd en v ss v + LTC1966 in1 v out = 4mv dc /a rms c ave 1 f 0.1 f in2 1966 ta08 v out ac current 75a max 50hz to 400hz out rtn gnd en v ss 100k 100k 10 t1: cr magnetics cr8348-2500-n www.crmagnetics.com t1 single supply rms current measurement 30 LTC1966 sn1966 1966fas si plified sche atic ww 2nd order ? s modulator in1 in2 en v dd + + output out rtn 30k bleed resistor for c ave c ave 1966 ss to bias control v ss gnd c1 c2 y1 y2 c12 c11 closed during shutdown c9 c10 c5 c3 c4 c6 c8 c7 a2 a1 31 LTC1966 sn1966 1966fas u package descriptio ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. msop (ms8) 0802 0.53 0.015 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.077) 0.254 (.010) 1.10 (.043) max 0.22 ?0.38 (.009 ?.015) typ 0.13 0.076 (.005 .003) 0.86 (.034) ref 0.65 (.0256) bsc 0 ?6 typ detail ? detail ? gauge plane 12 3 4 4.90 0.15 (1.93 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) note 4 0.52 (.206) ref 5.23 (.206) min 3.2 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.04 (.0165 .0015) typ 0.65 (.0256) bsc 32 LTC1966 sn1966 1966fas ? linear technology corporation 2001 lt/tp 1002 1k rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts part number description comments lt ? 1077 micropower, single supply precision op amp 48 m a i sy , 60 m v v os(max) , 450pa i os(max) lt1175-5 negative, C5v fixed, micropower ldo regulator 45 m a i q , available in so-8 or sot-223 lt1494 1.5 m a max, precision rail-to-rail i/o op amp 375 m v v os(max) , 100pa i os(max) lt1782 general purpose sot-23 rail-to-rail op amp 40 m a i sy , 800 m v v os(max) , 2na i os(max) lt1880 sot-23 rail-to-rail output precision op amp 1.2ma i sy , 150 m v v os(max) , 900pa i os(max) ltc2050 zero drift op amp in sot-23 750 m a i sy , 3 m v v os(max) , 75pa i b(max) lt2178/lt2178a 17 m a max, single supply precision dual op amp 14 m a i sy , 120 m v v os(max) , 350pa i os(max) ltc2402 2-channel, 24-bit, micropower, no latency ds tm adc 200 m a i sy , 4ppm inl, 10ppm tue ltc2420 20-bit, micropower, no latency ds adc in so-8 200 m a i sy , 8ppm inl, 16ppm tue ltc2422 2-channel, 20-bit, micropower, no latency ds adc dual channel version of ltc2420 no latency ds is a trademark of linear technology corporation. 2.5v supplies, single ended, dc-coupled rms-to-dc converter with shutdown v dd 2.5v 2.5v 2.5v 2.5v LTC1966 in1 dc output c ave 1 f 0.1 f x7r in2 1966 ta06 v out dc + ac input (1v peak ) out rtn gnd en v ss off 3 2v ?v on battery-powered single-ended ac-coupled rms-to-dc converter v dd ac input (1v peak ) LTC1966 in1 dc output c ave 1 f c c 0.1 f 0.1 f x7r in2 1966 ta07 v out out rtn gnd gnd lt1175cs8-5 shdn v in out 9v sense en v ss typical applicatio s u 5v LTC1966 in1 v out 4mv dc /a rms c ave 1 f in2 1966 ta09 v out ac current 75a max 50hz to 400hz out rtn gnd en v ss 10 t1: cr magnetics cr8348-2500-n www.crmagnetics.com ?v t1 v dd 5v 5v ?v ?v LTC1966 in1 c ave 1 f 0.1 f 1.5 f in2 1966 ta10 v out voltage noise in out rtn gnd en v ss 1mv dc 1 v rms noise v out = + 10k 100 100 100k bw 1khz to 100khz input sensitivity = 1 v rms typ 1/2 ltc6203 rms noise measurement 75a current measurement |
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